The present invention relates to an input/output switch apparatus for data storage and processing devices and systems. In particular, the present invention is directed to such a switch apparatus which is useful with content addressable or associative memories.
A content addressable or associative memory is a device which stores information. When a central control broadcasts information, the content addressable memory compares the information which it has stored with the broadcast information and indicates whether there is agreement or disagreement between the two.
Content addressable memories were first proposed in the 1950's. Since that time, they have been discussed extensively in the literature. In recent years, commercially available content addressable memories have appeared. A detailed description of the operation and features of content addressable memories and parallel processors is contained in a book by Caxton C. Foster, "Content Addressable Parallel Processors" (1976). Patents describing content addressable memories and parallel processors include U.S. Pat. Nos. 3,245,052 (Lewin); 3,387,274 (David); 3,540,002 (Clapper); 3,588,845 (Ling); 3,648,254 (Beausoleil); 3,681,762 (Minshull et al); 3,729,718 (Dufton et al); 3,913,075 (Vitalieu et al); 3,936,806 (Batcher); and 3,970,993 (Finnila).
The requirement for content addressable memories and parallel processors stems from the inherent performance limitations in conventional data base approaches.
In contrast to conventional techniques, content addressable memories have the capability of retrieving information directly, based on the attributes of the data itself. This is accomplished by including sufficient processing capability in the data storage medium to perform searching operations. As greater search and retrieval capability is provided in the memory circuits, there is an ever increasing need for greater capability in the input and output circuitry coupling the memory apparatus to the host system. In serial types of content addressable memories, the input/output (I/O) logic requirements for such are constrained to be serial. Such an I/O is not acceptable in a content addressable memory having parallel addressing capabilities and, as in the memory described here, where multiple address locations are likely to be selected in any search of the memory stored data base, there is a need for a fast transfer of the data to or from the host system.
In the extended capability content addressable memory (ECAM) described herein, the access to the stored data words is serial. The normal approach to handling a word transfer would be with a word parallel I/O except for the fact that the transfer rate potential of a word parallel bus cannot be sustained by the serial data available at a single word. Another approach would involve the physical partitioning of the ECAM into subsystems, each with their own I/O circuit logic. This has been found to introduce undue complexity in the control software and also to be subject to the problem of having all the searched-for data located in one subsystem which means the transfer from that subsystem will be the limiting factor on the transfer date.
To overcome the limitations of known options available for input/output transfers, the present apparatus has been provided to implement the desired functions in a high-speed manner using a simplified logic approach which lends itself to implementation using large scale integrated circuit techniques. In one preferred embodiment, the I/O switching circuit takes the form of a series of logical circuit blocks arranged in a triangular type functional switching means which yields a significant saving in complexity and in physical size.